1. Technical Field
The disclosure relates to DRAM memory systems. In particular, the disclosure relates to command scheduling in DDR SDRAM memory systems.
2. Description of the Prior Art
The primary goal in the design of high performance memory systems is to obtain maximum bandwidth with low request access latencies. However, constraints such as data bus synchronization overhead in DDRx SDRAM devices memory systems, where x is an integer greater than or equal to two, and constraints that limit peak power in DDR2 and DDR3 devices will significantly impact sustainable bandwidth in high performance DDRx SDRAM memory systems. Moreover, while DRAM device datarate increases with each new generation of DDRx SDRAM devices at the rate of 100% every three years, DRAM row cycle times are only decreasing at a rate of 7% per year. Collectively, these trends increase the difficulty of achieving maximum sustainable bandwidth from each successive generation of higher datarate DDRx SDRAM devices by increasing the ratio of DRAM row cycle time to data transport time. Previous studies have recognized and examined the importance of DRAM access scheduling but do not address the issue of data bus synchronization and power limiting constraints in DDRx SDRAM memory systems.
Previous work in the area of DRAM command scheduling examines the impact of data bus synchronization overhead, write-to-read turnaround times and row-to-row activation times, but does not address the four-bank-activation window limitation of tFAW, nor do any previous studies offer specific algorithms that deal with the conflicting requirements of these different overheads.